1. Field of the Invention
The present invention relates to a CMOS transistor and method of making the same, and more particularly, to a CMOS transistor having improved latch-up robustness and method of making the same.
2. Description of the Prior Art
Complementary Metal-Oxide Semiconductor (CMOS) transistor is composed of an NMOS transistor and a PMOS transistor. Please refer to FIG. 1. FIG. 1 is a schematic diagram illustrating a conventional CMOS transistor. As shown in FIG. 1, the CMOS transistor has a P type substrate 10, which includes a PMOS region 20 and an NMOS region 40 while viewed from top. The PMOS region 20 and the NMOS region 40 are isolated from each other by isolation structures 12. The PMOS region 20 includes an N well 22 disposed in the substrate 10, a gate dielectric layer 24 disposed on the surface of the substrate 10, a gate electrode 26 on the surface of the gate dielectric layer 24, two spacers 28 disposed alongside the gate electrode 26, and two P type source/drain doped regions 30 respectively disposed in the substrate 10 by both sides of the spacers 28. In addition, two lightly doped drains (LDD) 32 are disposed in the substrate 10 under the spacers 28, and two lightly doped pocket doped regions (also referred to as halo doped regions) 34 are positioned under the lightly doped drains 32.
The NMOS region 40 includes a P well 42 disposed in the substrate 10, a gate dielectric layer 44 disposed on the surface of the substrate 10, a gate electrode 46 disposed on the surface of the gate dielectric layer 44, two spacers 48 disposed alongside the gate electrode 46, two N type source/drain doped region 50 respectively disposed in the substrate 10 by both sides of the spacers 48. In addition, two lightly doped drains (LDD) 52 are disposed in the substrate 10 under the spacers 48.
The CMOS transistor has been widely used as a primary basic electronic device, however, latch-up phenomenon may occur when critical dimension improves if the PMOS transistor and the NMOS transistor are not well isolated. In addition, for some high current or high voltage ICs, e.g. analogue ICs or power management ICs (PMICs), latch-up is a critical issue to be improved.
Please refer to FIGS. 2-3, and FIG. 1 as well. FIG. 2 is a schematic diagram of a pnpn diode, and FIG. 3 is a current vs. voltage relation chart of a pnpn diode shown in FIG. 2. As shown in FIG. 1, the CMOS transistor is configured as an inverter for the purpose of testing latch-up. The P type source/drain doped region 30, the n well 22, and the P type substrate 10 in the PMOS device region 20 act as a vertical pnp bipolar junction transistor. On the other hand, the N type source/drain 50 and the p well 42 of the NMOS device region 40, and the n well 22 of the PMOS device region 20 act as a lateral npn bipolar junction transistor. Since the base of the vertical pnp bipolar junction transistor and the collector of the lateral npn bipolar junction transistor are electrically coupled, and the collector of the vertical pnp transistor and the base of the lateral npn bipolar junction transistor are electrically coupled, the base of any one bipolar junction transistor is driven by the other bipolar junction transistor. As a result, the vertical pnp bipolar junction transistor and the lateral npn transistor form a positive feedback loop.
The positive feedback loop can be regarded as a parasitic pnpn diode as shown in FIG. 2, and the current vs. voltage operational curve is shown in FIG. 3. The triggering current is IH, and when the current is greater than the triggering current IH, the pnpn diode is in an “on” state. Accordingly, latch-up will occur to the CMOS transistor. Once latch-up happens, the CMOS transistor will temporarily or even permanently fail. Therefore, it is a crucial issue to prevent latch-up in CMOS designs and fabrications.